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|e ppiak
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|a Matić, Bruno
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|a Optimiranje video-algoritama korištenjem naredaba ARM NEON i izvedbom u sklopovlju FPGA :
|b diplomski rad /
|c Bruno Matić ; [mentor Mario Kovač].
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|a Video Algorithms Optimization Using ARM NEON Instructions and FPGA Implementation
|i Naslov na engleskom:
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|a Zagreb,
|b B. Matić,
|c 2017.
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|a 35 str. ;
|c 30 cm +
|e CD-ROM
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|b diplomski studij
|c Fakultet elektrotehnike i računarstva u Zagrebu
|g smjer: Računalno inženjerstvo, šifra smjera: 55, datum predaje: 2017-06-29, datum završetka: 2017-07-03
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|a Sažetak na hrvatskom: U radu je proučen algoritam 2D DCT-a i algoritam interpolacije za normu H.265.
Uz pomoć PetaLinux i Vivado alata razvijene su dvije platforme za razvoj i ispitivanje zasnovan na Linux operativnom sustavu. Algoritam 2D DCT-a je optimiziran za što brže izvođenje na Zynq SoC-u kroz tri faze: optimiziranje (redizajniranje) samog algoritma, izvedba redizajniranog algoritma u C programskom jeziku i direktno u ARM strojnom kôdu, te konačna izvedba unutar FPGA sklopovlja putem SDSoC alata. Slična metoda optimizacije se predlaže i za algoritam interpolacije. Konačno optimalno rješenje jest hibridni sustav koji dio algoritma izvodi na procesoru ARM Cortex-A9 naredbama NEON, a dio akceleratorskim jezgrama unutar FPGA sklopovlja.
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|a Sažetak na engleskom: In this master thesis H.265 standard 2D DCT algorithm and interpolation algorithm were studied. By using PetaLinux and Vivado toolset two Linux based development and testing platforms were developed. 2D DCT algorithm was optimized for speed on Zynq SoC in three phases: optimizing (redesigning) the algorithm, implementation of redesigned algorithm in C programming language and directly in ARM assembly code and finally by implementing the algorithm in FPGA fabric trough SDSoC tool. Similar method of optimization is proposed for interpolation algorithm. Final optimal solution is a hybrid system where a part of the algorithm is executed on ARM Cortex-A9 processor using NEON instructions and the second part of the algorithm is executed on accelerator cores in FPGA fabric.
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|a Zynq
|a NEON
|a HEVC
|a H.265
|a DCT
|a interpolacija
|a HLS
|a akcelerator
|a Linux
|a SDSoC
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|a Zynq
|a NEON
|a HEVC
|a H.265
|a DCT
|a interpolation
|a HLS
|a accelerator
|a Linux
|a SDSoC
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|a Kovač, Mario
|4 ths
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|c Y
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|d 49387
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