Design and test technology for dependable systems-on-chip
"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--
| Permalink: | http://skupnikatalog.nsk.hr/Record/fer.KOHA-OAI-FER:41310/Similar |
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| Ostali autori: | Ubar, Raimund, 1941- (-), Raik, Jaan, 1972-, Vierhaus, Heinrich Theodor, 1951- |
| Vrsta građe: | Knjiga |
| Jezik: | eng |
| Impresum: |
Hershey, PA :
Information Science Reference,
2011.
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| Predmet: |
APA stil citiranja
Ubar, R., Raik, J., & Vierhaus, H. T. (2011). Design and test technology for dependable systems-on-chip: Design and test technology for dependable systems-on-chip. Hershey, PA: Information Science Reference.
Chicago stil citiranjaUbar, Raimund, Jaan Raik, and Heinrich Theodor Vierhaus. Design and test technology for dependable systems-on-chip: Design and test technology for dependable systems-on-chip. Hershey, PA: Information Science Reference, 2011.
MLA stil citiranjaUbar, Raimund, Jaan Raik, and Heinrich Theodor Vierhaus. Design and test technology for dependable systems-on-chip: Design and test technology for dependable systems-on-chip. Hershey, PA: Information Science Reference, 2011.