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|9 (HR-ZaNSK)552111
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|a 004.424.5.021
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|a Mumolo, Enzo
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|a VHDL design of a scalable VLSI sorting device based on pipelined computation /
|c Enzo Mumolo, Gabriele Capello and Massimiliano Nolich.
|
| 246 |
1 |
3 |
|a Very High Speed Integrated Circuit Hardware Description Language
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| 300 |
|
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|b Ilustr.
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| 504 |
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|a Bilješke uz tekst ; bibliografija: 29 jed
|
| 650 |
|
7 |
|a Algoritmi za sortiranje
|v Analiza
|2 nskps
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| 700 |
1 |
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|a Capello, Gabriele
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| 700 |
1 |
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|a Nolich, Massimiliano
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| 773 |
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|t CIT. Journal of computing and information technology
|x 1330-1136
|g 12 (2004), 1 ; str. 1-14
|w nsk.(HR-ZaNSK)000018028
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| 981 |
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|z B3/04
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