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| LEADER |
03661cam a22003378a 4500 |
| 005 |
20150424173318.0 |
| 008 |
100910s2011 flu b 001 0 eng |
| 010 |
|
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|a 2010036073
|
| 020 |
|
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|a 9781439837108 (hardback)
|
| 040 |
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|a DLC
|c DLC
|b hrv
|d HR-ZaFER
|e ppiak
|
| 042 |
|
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|a pcc
|
| 050 |
0 |
0 |
|a TK5105.546
|b .D476 2011
|
| 082 |
0 |
0 |
|a 621.3815/31
|2 22
|
| 084 |
|
|
|a COM011000
|a COM059000
|2 bisacsh
|
| 245 |
0 |
0 |
|a Designing network on-chip architectures in the nanoscale era /
|c [edited by] Jose Flich, Davide Bertozzi.
|
| 260 |
|
|
|a Boca Raton, FL :
|b Chapman and Hall/CRC,
|c 2011.
|
| 263 |
|
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|a 1012
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| 300 |
|
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|a xxxviii, 490 str.:
|b ilustr.;
|c 24 cm.
|
| 490 |
0 |
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|a Chapman & Hall/CRC computational science
|
| 504 |
|
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|a Includes bibliographical references and index.
|
| 520 |
|
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|a "Paving the way for the use of network on-chip architectures in 2015 platforms, this book presents the industrial requirements for such long-term platforms as well as the main research findings for technology-aware architecture design. It covers homogeneous design techniques and guidelines, including the solutions that are most appealing to the industry and best suited to meet the requirements of on-chip integration. Each chapter deals with a specific key architecture design, including fault tolerant design, topology selection, dynamic voltage and frequency scaling, synchronization, network on-chip resources exposed to the architecture, routing algorithms, and collective communication"--
|
| 520 |
|
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|a "Chip Multiprocessors (CMPs) are diving very aggressively into the marketplace since past efforts to speed up processor architectures in ways that do not modify the basic von Neumann computing model have encountered hard limits. The power consumption of the chip becomes the limiting factor and sets the rules for future CMP systems. As a result, the microprocessor industry is today leading the development of multicore and many-core architectures where, as the number of cores increases, efficient communication among them and with off-chip resources becomes key to achieve the intended performance scalability. This trend has helped overcome the skepticism of some system architects to embrace on-chip interconnection networks as a key enabler for effective system integration. Networks-on-chip (NoCs) make performance scalability more a matter of instantiation and connectivity rather than increasing complexity of specific architecture building blocks. This book comes as a timely and welcome addition to the wide spectrum of available NoC literature, as it has been designed with the purpose of describing in a coherent and well-grounded fashion the foundation of NoC technology, above and beyond a simple overview of research ideas and/or design experiences. It covers in depth architectural and implementation concepts and gives clear guidelines on how to design the key network component, providing strong guidance in a research field that is starting to stabilize, bringing "sense and simplicity" and teaching hard lessons from the design trenches. The book also covers upcoming research and development trends, such as vertical integration and variation tolerant design. It is a much needed "how-to" guide and an ideal stepping stone for the next ten years of NoC evolution"--
|
| 650 |
|
0 |
|a Networks on a chip.
|
| 650 |
|
7 |
|a COMPUTERS / Systems Architecture / General
|2 bisacsh.
|
| 650 |
|
7 |
|a COMPUTERS / Computer Engineering
|2 bisacsh.
|
| 700 |
1 |
|
|a Flich, Jose.
|
| 700 |
1 |
|
|a Bertozzi, Davide.
|
| 906 |
|
|
|a 7
|b cbc
|c orignew
|d 1
|e ecip
|f 20
|g y-gencatlg
|
| 942 |
|
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|2 udc
|c K
|
| 955 |
|
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|b xh57 2010-09-10
|c xh57 2010-09-10 ONIX to subj. cat.
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| 999 |
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|c 44103
|d 44103
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