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01470fam a2200325 a 4500 |
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20130713153803.0 |
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920812s1993 maua b 001 0 eng |
| 010 |
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|a 92029798
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| 020 |
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|a 0792392817
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| 035 |
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|a (OCoLC)26541403
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| 035 |
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|a (OCoLC)ocm26541403
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| 035 |
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|a (NNC)1177071
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| 040 |
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|a DLC
|c DLC
|d DLC
|b hrv
|e ppiak
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| 050 |
0 |
0 |
|a TK7871.99.M44
|b S37 1992
|
| 082 |
0 |
0 |
|a 621.39/5
|2 20
|
| 100 |
1 |
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|a Sapatnekar, Sachin S.,
|d 1967-
|
| 245 |
0 |
0 |
|a Design automation for timing-driven layout synthesis /
|c by Sachin S. Sapatnekar, Sung-Mo (Steve) Kang.
|
| 260 |
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|a Boston :
|b Kluwer Academic Publishers,
|c c1993.
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| 300 |
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|a xx, 269 p. :
|b ill. ;
|c 25 cm.
|
| 490 |
1 |
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|a The Kluwer international series in engineering and computer science ;
|v SECS198.
|a VLSI, computer architecture, and digital signal processing
|
| 504 |
|
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|a Includes bibliographical references (p. 247-266) and index.
|
| 650 |
|
0 |
|a Metal oxide semiconductors, Complementary
|x Design and construction
|x Data processing.
|
| 650 |
|
0 |
|a Integrated circuits
|x Very large scale integration
|x Design and construction
|x Data processing.
|
| 650 |
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0 |
|a Computer-aided design.
|
| 700 |
1 |
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|a Kang, Sung-Mo,
|d 1945-
|
| 830 |
|
0 |
|a Kluwer international series in engineering and computer science ;
|v SECS 198.
|
| 830 |
|
0 |
|a Kluwer international series in engineering and computer science.
|p VLSI, computer architecture, and digital signal processing.
|
| 900 |
|
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|a AUTH
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| 942 |
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|2 udc
|c K
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| 999 |
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|c 40630
|d 40630
|