LEADER 01470fam a2200325 a 4500
005 20130713153803.0
008 920812s1993 maua b 001 0 eng
010 |a  92029798  
020 |a 0792392817 
035 |a (OCoLC)26541403 
035 |a (OCoLC)ocm26541403 
035 |a (NNC)1177071 
040 |a DLC  |c DLC  |d DLC  |b hrv  |e ppiak 
050 0 0 |a TK7871.99.M44  |b S37 1992 
082 0 0 |a 621.39/5  |2 20 
100 1 |a Sapatnekar, Sachin S.,  |d 1967- 
245 0 0 |a Design automation for timing-driven layout synthesis /  |c by Sachin S. Sapatnekar, Sung-Mo (Steve) Kang. 
260 |a Boston :  |b Kluwer Academic Publishers,  |c c1993. 
300 |a xx, 269 p. :  |b ill. ;  |c 25 cm. 
490 1 |a The Kluwer international series in engineering and computer science ;  |v SECS198.  |a VLSI, computer architecture, and digital signal processing 
504 |a Includes bibliographical references (p. 247-266) and index. 
650 0 |a Metal oxide semiconductors, Complementary  |x Design and construction  |x Data processing. 
650 0 |a Integrated circuits  |x Very large scale integration  |x Design and construction  |x Data processing. 
650 0 |a Computer-aided design. 
700 1 |a Kang, Sung-Mo,  |d 1945- 
830 0 |a Kluwer international series in engineering and computer science ;  |v SECS 198. 
830 0 |a Kluwer international series in engineering and computer science.  |p VLSI, computer architecture, and digital signal processing. 
900 |a AUTH 
942 |2 udc  |c K 
999 |c 40630  |d 40630