LEADER 01318cam a22003014a 4500
005 20130713153402.0
008 990104s1999 mau b 001 0 eng
010 |a  99012430  
020 |a 0792384520 (alk. paper) 
040 |a DLC  |c DLC  |d HR-ZaFER  |b hrv  |e ppiak 
042 |a pcc 
050 0 0 |a TK7871.99.M44  |b U92 1999 
082 0 0 |a 621.39/732  |2 21 
100 1 |a Uyemura, John P.  |q (John Paul),  |d 1952- 
245 1 0 |a CMOS logic circuit design /  |c John P. Uyemura. 
260 |a Boston :  |b Kluwer Academic Publishers,  |c c1999. 
300 |a xviii, 528 p. ;  |c 27 cm. 
504 |a Includes bibliographical references and index. 
650 0 |a Metal oxide semiconductors, Complementary  |x Design and construction. 
650 0 |a Logic design. 
650 0 |a Digital integrated circuits  |x Design and construction. 
650 0 |a Integrated circuits  |x Very large scale integration  |x Design and construction. 
856 4 2 |3 Publisher description  |u http://www.loc.gov/catdir/enhancements/fy0821/99012430-d.html 
856 4 1 |3 Table of contents only  |u http://www.loc.gov/catdir/enhancements/fy0821/99012430-t.html 
906 |a 7  |b cbu  |c orignew  |d 1  |e ocip  |f 19  |g y-gencatlg 
942 |2 udc  |c K 
955 |a pb07 to ja00 01-05-99; jf05 to subj. 01/06/99; jf08 01-06-99 to SL;jf12 01-06-99 to ddc; CIP ver. jf05 to sl 04/16/99 
999 |c 34482  |d 34482